Power supply lines in a semiconductor integrated circuit chip supply current to charge and discharge active and passive devices in the integrated circuit. For example, digital complementary metal-oxide-semiconductor (CMOS) circuits draw current when the clock makes a transition. During the operation of circuits, the power supply lines must supply transient currents with a relatively high intensity, and can result in voltage noise on the power supply lines. The voltage on the power supply line will fluctuate when the fluctuation time of the transient current is short or when its parasitic inductance or parasitic resistance is large.
In state-of-the-art circuits, the operational frequency of the integrated circuit is in the order of several hundreds of mega-hertz (MHz) to several giga-hertz (GHz). In such circuits, the rising time of clock signals is very short, so that voltage fluctuations in the supply line can be very large. Undesired voltage fluctuations in the power supply line powering a circuit can cause noise on its internal signals and degrade noise margins. The degradation of noise margins can reduce circuit reliability or even cause circuit malfunction.
To reduce the magnitude of voltage fluctuations in the power supply lines, filtering or decoupling capacitors are usually used between the terminals of different power supply lines or between terminals of power supply line and the ground line. Decoupling capacitors act as charge reservoirs that additionally supply currents to circuits when required to prevent momentary drops in supply voltage.
FIG. 1 shows a circuit diagram containing these decoupling capacitors. Capacitor C1 is a decoupling capacitor that is inserted between a power supply line VDD and the ground line GND. Most chips employ more than one power supply line, and may have a different power supply line OVDD for the output circuits that interface with external circuits. Capacitor C2 is a decoupling capacitor that is inserted between the output voltage supply line OVDD and the ground line GND. Capacitor C3 is a decoupling capacitor that is inserted between the supply line VDD and the output voltage supply line OVDD. These decoupling capacitors are usually placed as close as possible to the transient current source or sink.
Decoupling capacitors are used in integrated chips employing both bulk and silicon-on-insulator substrates. However, the role of decoupling capacitors is more important in a silicon-on-insulator chip than in a bulk silicon chip due to the following reason. Integrated chips fabricated on bulk substrates can naturally decouple the power supply potential and the ground potential due to the presence of inherent depletion capacitances between the doped wells and the bulk substrate. Compared to bulk substrates, silicon-on-insulator chips have very low on-chip decoupling capacitance between the power supply lines and ground.
U.S. Pat. No. 6,558,998 entitled “SOI type integrated circuit with a decoupling capacity and process for embodiment of such a circuit” issued to Belleville et al. describes a decoupling capacitor that is formed with the formation of silicon-on-insulator substrates. While that capacitor may be formed with a large area or large capacitance, it is formed together with the substrate, which means that the substrate has to be customized for each different circuit design.